A useful function in many integrated circuits, such as data processors, is a magnitude comparison of two numbers. For example, a data processor core may be integrated with several different on-chip peripheral circuits, such as on-chip memory. For different integrated circuit designs using the data processor core, the size of the on-chip memory varies. The data processor core must determine whether a memory access cycle is to the on-chip memory or to off-chip memory. The data processor core makes this determination by performing a magnitude comparison between critical address bits and a preprogrammed address space size. If the magnitude comparator detects that the address is less than or equal to pre-programmed address space size, then the access is to internal memory. Otherwise, the access is to external memory. Since data processor cores using current technology may operate with clock speeds of approximately 40 MHz, the magnitude comparator must be very fast to avoid delaying the memory access.
There are two types of known magnitude comparator circuits. The first type is a sequential magnitude comparator, such as the AMD 9324 5-bit comparator. The sequential comparator first compares the most-significant bit of each of the two operands. Logic circuitry determines whether the first operand is larger than, equal to, or less than the second operand. If the most-significant bits are not equal to each other, the magnitude comparator can then provide an output signal representing the result of the comparison. However, if the bits are equal to each other, then the comparison is indeterminate and must proceed to the next-most-significant bit position. Likewise, the results of this comparison may determine the overall result, but it may be necessary for the comparison to proceed to the next-most-significant bit, and so on, until the least-significant bits are compared. In the worst case, the comparison will not be complete until all bits are compared, requiring approximately seven logic levels for a five-bit comparator.
The second type of magnitude comparator is a bit-cell magnitude comparator. The bit-cell magnitude comparator simultaneously compares corresponding bits from each bit position of the two operands. Each bit cell activates one of three output signals, a less-than signal designated "LT", a greater than signal designated "GT", or an equal to signal designated "EQ". Corresponding LT, GT, and EQ signals from all bit cells are then combined using random logic to provide overall LT, GT, and EQ signals. While this design may reduce the number of logic levels below that of the sequential design, it may also require the use of multiple-input logic gates, which increase switching time. For example, a five-bit magnitude comparator may be implemented in approximately five logic levels by using multiple-input logic gates.